Electronics and Embedded Systems · CHAPTER 5 / 5
Level: introductory undergraduate · Study session: 15–20 minutes including practice.
Learning outcome: Choose a bus using wiring, addressing and timing requirements.
Before you begin: Complete earlier chapters in this discipline; revise algebra and units as needed.
1. Understand the idea
UART is asynchronous and commonly point-to-point. I²C uses addressed devices on shared clock and data lines with pull-ups. SPI uses a clock and device selection with separate data directions in a common arrangement. Voltage compatibility, cable length, clock rate and device timing matter more than protocol popularity.
2. Write the model
UART 8N1: 10 transmitted bits per data byte
Define the symbols from the worked case before substituting values. Keep units consistent, record the assumptions and round only after the calculation.
3. Follow a worked example
At 9600 bit/s with 8N1 framing, an ideal continuous stream carries at most 960 data bytes/s. Sending 100 bytes takes approximately 0.104 s before software delays or protocol overhead.
4. Explore the model
| Baud (bit/s) | 8N1 payload ceiling (bytes/s) | 100-byte time (s) |
|---|---|---|
| 9600 | 960 | 0.104167 |
| 19200 | 1920 | 0.052083 |
| 115200 | 11520 | 0.008681 |
Sweep baud and observe ideal transfer duration. Keep framing fixed so the comparison is fair.
5. Reproduce it yourself
- Copy the input cases into Excel or a notebook and name each quantity and unit.
- Recalculate each result from the stated equation or rule. For qualitative cases, explain the state or partition decision instead.
- Change one input, predict the direction of change, then calculate again.
- Write one sentence explaining where the model stops being valid.
6. Check your understanding
Why is 9600 baud not 9600 payload bytes per second?
Reveal the answer and check your work
Each 8N1 data byte occupies 10 bit periods.
Compare your result, units and reasoning. If they differ, return to the equation and test the worked case first.
7. Common mistake
Do not connect incompatible logic voltage levels directly.
Further study and academic note
Explore the discipline reference and further learning resources. This is an original IIMEEE introductory teaching note with synthetic examples; it is not a peer-reviewed research result or a professional design specification. Figures were constructed from the listed teaching cases. Resource links support further study and do not imply endorsement.
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